The field of the present invention is computer assisted design (CAD) systems and methods, and more particularly, circuit emulation systems and methods.
Recently, much attention in the computer assisted design (CAD) field, has been directed to the implementation of digital circuit emulation systems and methods. Exemplary emulation systems are disclosed in U.S. Pat. No. 5,109,353, entitled "Apparatus for Emulation of Electronic Hardware System" issued Apr. 28, 1992 to Sample et. al., and U.S. Pat. No. 5,036,473, entitled "Method of Using Electronically Reconfigurable Logic Circuits" issued Jul. 30, 1991 to Butts et al., which patents are hereby incorporated by reference.
In short, the above identified patents disclose systems and methods which utilize field programmable gate array integrated circuits to emulate digital circuit or system designs. Since their initial introduction to the circuit design and verification system market in late 1988, emulation systems have enjoyed substantial commercial success.
However, as the field of emulation has developed, it has been recognized that the presence of hold time violations in a configured circuit or system can pose an impediment to efficient circuit emulation. Accordingly, it is believed that a system and method capable of minimizing hold time violations in a configured circuit or system design would be highly desirable to those in the CAD field.